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Real-time machine learning algorithms have shown their importance in multiple domains. There are applications that require machine learning from a continuous input stream of data. Dataflow computational models can be suitable for modelling such algorithms for the following reasons. A) They will show the algorithms' main building blocks and allow reconfiguration that helps in generating multiple hardware architectures to execute a specific machine learning model. B) They exploit possible parallelism that can impact the algorithm performance positively. In this project, it is required to build a tool to generate a dataflow model and construct architectures for such algorithms, while minimizing latency or meeting a specific deadline under area and power constraints. The tools should generate VHDL or Verilog code of such architectures to evaluate them.
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