View source for Publications:High-level programming of coarse-grained reconfigurable architectures

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{{PublicationSetupTemplate|Author=Zain Ul-Abdin
|PID=235543
|Name=Zain-ul-Abdin,  [zaiabd] (Högskolan i Halmstad [2804], Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE) [3905], Halmstad Embedded and Intelligent Systems Research (EIS) [3938], Inbyggda system (CERES) [3939])
|Title=High-level programming of coarse-grained reconfigurable architectures
|PublicationType=Conference Paper
|ContentType=Refereegranskat
|Language=eng
|Journal=
|JournalISSN=
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|Volume=
|Issue=
|HostPublication=19<sup>th</sup> International Conference on Field Programmable Logic and Applications : (FPL), proceedings, Prague, Czech Republic, August 31-September 2, 2009
|Conference=19th International Conference on Field Programmable Logic and Applications, Prague, Czech Republic, August 31-September 2, 2009
|StartPage=713
|EndPage=714
|Year=2009
|Edition=
|Pages=
|City=Piscataway, N.J.
|Publisher=IEEE
|Series=International Conference on Field Programmable Logic and Applications ; 2009
|SeriesISSN=1946-1488
|ISBN=978-1-4244-3892-1
|Urls=
|ISRN=
|DOI=http://dx.doi.org/10.1109/FPL.2009.5272337
|ISI=000277506300130
|PMID=
|ScopusId=2-s2.0-70449889832
|NBN=urn:nbn:se:hh:diva-87
|LocalId=
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|Keywords=Coarse-Grained Reconfigurable Architectures
|Categories=Datorteknik (10206)
|ResearchSubjects=
|Projects=Embedded Parallel Computing
|Notes=©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
|Abstract=<p>We propose that, in order to meet high computational demands, the  application development has to be based on suitable models of  computations that will lead to scalable and reusable implementations.  The models should enhance the understanding of the application and at  the same time enable the developer to organize the computations so that  they can be efficiently mapped to the target reconfigurable  architecture. The goal of the thesis is to propose methods to program  future coarse-grained reconfigurable architecttures in a productive  manner in such a way as to achieve energy efficient mapping with  improved performance.</p>
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|CreatedDate=2009-09-16
|PublicationDate=2009-09-18
|LastUpdated=2011-04-28
|diva=http://hh.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:235543}}
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