View source for Publications:Manycore performance analysis using timed configuration graphs

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{{PublicationSetupTemplate|Author=Jerker Bengtsson, Bertil Svensson
|PID=353074
|Name=Bengtsson, Jerker [jebe] (Högskolan i Halmstad [2804], Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE) [3905], Halmstad Embedded and Intelligent Systems Research (EIS) [3938], Centrum för forskning om inbyggda system (CERES) [6702]);Svensson, Bertil [bertil] (Högskolan i Halmstad [2804], Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE) [3905], Halmstad Embedded and Intelligent Systems Research (EIS) [3938], Centrum för forskning om inbyggda system (CERES) [6702])
|Title=Manycore performance analysis using timed configuration graphs
|PublicationType=Conference Paper
|ContentType=Refereegranskat
|Language=eng
|Journal=
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|HostPublication=International Symposium on Systems, Architectures, Modeling, and Simulation, 2009. SAMOS '09
|Conference=2009 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2009, Samos, 20 - 23 July, 2009
|StartPage=108
|EndPage=117
|Year=2009
|Edition=
|Pages=
|City=Piscataway, N.J.
|Publisher=IEEE Press
|Series=
|SeriesISSN=
|ISBN=978-1-4244-4502-8
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|ISRN=
|DOI=http://dx.doi.org/10.1109/ICSAMOS.2009.5289221
|ISI=000276377000014
|PMID=
|ScopusId=2-s2.0-71949094275
|NBN=urn:nbn:se:hh:diva-5987
|LocalId=
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|Keywords=graphs;microcomputers;parallel architectures;parallel programming;program compilers;software performance evaluation;task analysis
|Categories=Datorteknik (10206)
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|Notes=<p>©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.</p>
|Abstract=<p>The programming complexity of increasingly parallel processors calls for new tools to assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed to form part of a tool which is intended for iteratively tuning the mapping of dataflow graphs onto manycores. One of the models is used for capturing the essentials of manycores that are identified as suitable for signal processing and which we use as target architectures. Another model is the intermediate representation in the form of a timed configuration graph, describing the mapping of a dataflow graph onto a machine model. Moreover, this IR can be used for performance evaluation using abstract interpretation. We demonstrate how the models can be configured and applied in order to map applications on the Raw processor. Furthermore, we report promising results on the accuracy of performance predictions produced by our tool. It is also demonstrated that the tool can be used to rank different mappings with respect to optimisation on throughput and end-to-end latency.</p>
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|CreatedDate=2010-09-23
|PublicationDate=2010-09-23
|LastUpdated=2012-09-22
|diva=http://hh.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:353074}}
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