View source for Publications:Static Consistency Checking for Verilog Wire Interconnects

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{{PublicationSetupTemplate|Author=Walid Taha, Cherif Salama, Gregory Malecha, Jim Grundy, John O'Leary
|PID=711469
|Name=Taha, Walid [waltah] (Rice University) (The Effective Modeling Group);Salama, Cherif (Rice University);Malecha, Gregory (Rice University);Grundy, Jim;O'Leary, John
|Title=Static Consistency Checking for Verilog Wire Interconnects
|PublicationType=Journal Paper
|ContentType=Refereegranskat
|Language=eng
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|Status=published
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|Year=2011
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|NBN=urn:nbn:se:hh:diva-25010
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|Categories=Data- och informationsvetenskap (102)
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|Abstract=<p>The Verilog hardware description language has padding semantics that allow designers to write descriptions where wires of different bit widths can be interconnected. However, many of these connections are nothing more than bugs inadvertently introduced by the designer and often result in circuits that behave incorrectly or use more resources than required. A similar problem occurs when wires are incorrectly indexed by values (or ranges) that exceed their bounds. These two problems are exacerbated by generate blocks. While desirable for reusability and conciseness, the use of generate blocks to describe circuit families only makes the situation worse as it hides such inconsistencies making them harder to detect. Inconsistencies in the generated code are only exposed after elaboration when the code is fully-expanded.</p><p>In this paper we show that these inconsistencies can be pinned down prior to elaboration using static analysis.We combine dependent types and constraint generation to reduce the problem of detecting the aforementioned inconsistencies to a satisfiability problem. Once reduced, the problem can easily be solved with a standard satisfiability modulo theories (SMT) solver. In addition, this technique allows us to detect unreachable code when it resides in a block guarded by an unsatisfiable set of constraints. To illustrate these ideas, we develop a type system for Featherweight Verilog (FV), a core calculus of structural Verilog with generative constructs and previously defined elaboration semantics. We prove that a well-typed FV description will always elaborate into an inconsistency-free description. We also provide a freely-available implementation demonstrating our approach.</p>
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|CreatedDate=2014-04-10
|PublicationDate=2014-04-10
|LastUpdated=2014-04-15
|diva=http://hh.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:711469}}
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