View source for Publications:Synthesizable High Level Hardware Descriptions

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{{PublicationSetupTemplate|Author=Jennifer Gillenwater, Gregory Malecha, Cherif Salama, Angela Yun Zhu, Walid Taha, Jim Grundy, John O’Leary
|PID=588246
|Name=Gillenwater, Jennifer (Rice University, 6100 Main St, Houston, TX 77005, United States);Malecha, Gregory (Rice University, 6100 Main St, Houston, TX 77005, United States);Salama, Cherif (Rice University, 6100 Main St, Houston, TX 77005, United States);Zhu, Angela Yun (Rice University, 6100 Main St, Houston, TX 77005, United States);Taha, Walid [waltah] (Rice University);Grundy, Jim (Intel Strategic CAD Labs, 2501 NW 229th Ave, Hillsboro, OR 97124, United States);O’Leary, John (Intel Strategic CAD Labs, 2501 NW 229th Ave, Hillsboro, OR 97124, United States)
|Title=Synthesizable High Level Hardware Descriptions
|PublicationType=Journal Paper
|ContentType=Refereegranskat
|Language=eng
|Journal=New generation computing
|JournalISSN=0288-3635
|Status=published
|Volume=28
|Issue=4
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|StartPage=339
|EndPage=369
|Year=2010
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|Pages=
|City=New York
|Publisher=Springer-Verlag New York
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|DOI=http://dx.doi.org/10.1007/s00354-008-0093-1
|ISI=000284289400002
|PMID=
|ScopusId=2-s2.0-78650128272
|NBN=urn:nbn:se:hh:diva-20944
|LocalId=
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|Keywords=Code Generation;Hardware Description Languages;Statically Typed Two-Level Languages;Synthesizability;Verilog Elaboration.
|Categories=Datorsystem (20206)
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|Abstract=<p>Modern hardware description languages support code generation constructs like generate/endgenerate in Verilog. These constructs are used to describe regular or parameterized hardware designsand, when used eﬀectively, can make hardware descriptions shorter, moreunderstandable, and more reusable. In practice, however, designers avoidthese abstractions because it is diﬃcult to understand and predict theproperties of the generated code. Is the generated code even type safe?Is it synthesizable? What physical resources (e.g. combinatorial gatesand ﬂip-ﬂops) does it require? It is often impossible to answer thesequestions without ﬁrst generating the fully-expanded code. In the Verilog and VHDL communities, this generation process is referred to as elaboration.This paper proposes a disciplined approach to elaboration in Verilog.∗1 By viewing Verilog as a statically typed two-level language, we are able to reﬂect the distinction between values that are known at elaborationtime and values that are part of the circuit computation. This distinctionis crucial for determining whether generative constructs, such as iterationand module parameters, are used in a synthesizable manner. This allowsus to develop a static type system that guarantees synthesizability. Thetype system achieves safety by performing additional checking on generative constructs and array indices. To illustrate this approach, we developa core calculus for Verilog that we call Featherweight Verilog (FV) andan associated static type system. We formally deﬁne a preprocessing stepanalogous to the elaboration phase of Verilog, and the kinds of errors thatcan occur during this phase. Finally, we show that a well-typed designcannot cause preprocessing errors, and that the result of its elaborationis always a synthesizable circuit.</p>
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|CreatedDate=2013-01-14
|PublicationDate=2013-01-15
|LastUpdated=2013-01-16
|diva=http://hh.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:588246}}
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