View source for Publications:Two-level Reconfigurable Architecture for High-Performance Signal Processing

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{{PublicationSetupTemplate|Author=Dennis Johnsson, Jerker Bengtsson, Bertil Svensson
|PID=353083
|Name=Johnsson, Dennis (Högskolan i Halmstad [2804], Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE) [3905], Halmstad Embedded and Intelligent Systems Research (EIS) [3938], Centrum för forskning om inbyggda system (CERES) [6702]);Bengtsson, Jerker [jebe] (Högskolan i Halmstad [2804], Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE) [3905], Halmstad Embedded and Intelligent Systems Research (EIS) [3938], Centrum för forskning om inbyggda system (CERES) [6702]);Svensson, Bertil [bertil] (Högskolan i Halmstad [2804], Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE) [3905], Halmstad Embedded and Intelligent Systems Research (EIS) [3938], Centrum för forskning om inbyggda system (CERES) [6702])
|Title=Two-level Reconfigurable Architecture for High-Performance Signal Processing
|PublicationType=Conference Paper
|ContentType=Refereegranskat
|Language=eng
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|HostPublication=ERSA'04, The 2004 International Conference on Engineering of Reconfigurable Systems and Algorithms : The 2004 International MultiConference in Computer Science and Computer Engineering
|Conference=International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA’04, Las Vegas, Nevada, June 2004
|StartPage=177
|EndPage=183
|Year=2004
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|Publisher=CSREA Press
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|NBN=urn:nbn:se:hh:diva-5991
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|Categories=Datorteknik (10206)
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|CreatedDate=2010-09-23
|PublicationDate=2010-09-23
|LastUpdated=2013-11-15
|diva=http://hh.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:353083}}
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