Ceres at 08:00, 11 October 2016

2016-10-11T08:00:14Z

Ceres: Created page with "{{StudentProjectTemplate |Title=Automatic Testing of Systems on Chip |Summary=The goal of this project is to gather necessary information needed for automatically generating a..."

2014-10-21T13:38:07Z

Created page with "{{StudentProjectTemplate |Title=Automatic Testing of Systems on Chip |Summary=The goal of this project is to gather necessary information needed for automatically generating a..."

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{{StudentProjectTemplate
|Title=Automatic Testing of Systems on Chip
|Summary=The goal of this project is to gather necessary information needed for automatically generating assertions and C-test cases for connectivity checks and integration tests when verifying a System On Chip.
|Author=Ericsson
|Supervisor=Mohammad Reza Mousavi, In cooperation with Ericsson Lund
|Level=Master
|Status=Open
}}
As a master thesis student you will engage in a thesis where the scope is divided in feasibility, planning, implementation, proof of concept and finally a report. You will develop a product with the ambition to have in integrated into our current verification flow and the work should include development activities such as requirement analysis, design, integration, verification, and product documentation.

You will be a part of a team which is responsible for ASIC Level Verification, creation of test benches and DFT Verification. The goal of the team is to verify that the functional requirements of our subsystems are fulfilled before tape-out of the digital ASIC.

Scope of the thesis is to gather (preferably in a DB) all necessary information (hierarchy, connectivity, signal/port types, verification probes, register descriptions, etc.) needed for automatically generating assertions and C-test cases for connectivity checks and integration tests when verifying a System On Chip. This, to increase our efficiency and enable us to spend more time on use case verification scenarios going forward. The development activities will focus on developing a translator (connectivity/reg descr/ver data/reqs/ -> DB) and a generator (DB -> test SW templates/assertions for Formal Verification).

'''Required Competence'''

* Knowledge of hardware design (VHDL/Verilog)
* Experience from Python or similar scripting languages
* Basic understanding and experience from working with databases (preferably graph-db)
* Experience from RTL simulators
* Trouble shooting and debugging capabilities
* Knowledge sharing, collaboration skills and a positive attitude
* Communication skills (Written and spoken English skills are required)
* Education level: Master of Science or similar

'''Desired Competence'''

* Good programming skills (C)
* System Verilog skills
* Experience in Digital ASIC System Level Verification
* Experience in WCDMA, GSM and/or LTE systems

@@ Line 1: / Line 1: @@
 {{StudentProjectTemplate
 |Summary=The goal of this project is to gather necessary information needed for automatically generating assertions and C-test cases for connectivity checks and integration tests when verifying a System On Chip.
 |Supervisor=Mohammad Reza Mousavi, In cooperation with Ericsson Lund
 |Level=Master
-|Status=Open
+|Status=Finished
 }}
 As a master thesis student you will engage in a thesis where the scope is divided in feasibility, planning, implementation, proof of concept and finally a report. You will develop a product with the ambition to have in integrated into our current verification flow and the work should include development activities such as requirement analysis, design, integration, verification, and product documentation.

Automatic Testing of Systems on Chip - Revision history

Ceres at 08:00, 11 October 2016

Ceres: Created page with "{{StudentProjectTemplate |Title=Automatic Testing of Systems on Chip |Summary=The goal of this project is to gather necessary information needed for automatically generating a..."