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		<title>HiPEC - Revision history</title>
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		<updated>2026-05-04T09:34:11Z</updated>
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	<entry>
		<id>https://wiki.hh.se/ceres/index.php?title=HiPEC&amp;diff=3065&amp;oldid=prev</id>
		<title>Slawek: Created page with &quot;{{ResearchProjInfo |Title=HiPEC |ContactInformation=Veronica Gaspes |ShortDescription=High Performance Embedded Computing |Description=Parallelism is the main way to provide s...&quot;</title>
		<link rel="alternate" type="text/html" href="https://wiki.hh.se/ceres/index.php?title=HiPEC&amp;diff=3065&amp;oldid=prev"/>
				<updated>2014-06-23T09:23:12Z</updated>
		
		<summary type="html">&lt;p&gt;Created page with &amp;quot;{{ResearchProjInfo |Title=HiPEC |ContactInformation=Veronica Gaspes |ShortDescription=High Performance Embedded Computing |Description=Parallelism is the main way to provide s...&amp;quot;&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;{{ResearchProjInfo&lt;br /&gt;
|Title=HiPEC&lt;br /&gt;
|ContactInformation=Veronica Gaspes&lt;br /&gt;
|ShortDescription=High Performance Embedded Computing&lt;br /&gt;
|Description=Parallelism is the main way to provide significant performance improvement of embedded systems while&lt;br /&gt;
keeping energy consumption low. Streaming applications are good candidates for parallelization since&lt;br /&gt;
they are regular and exhibit data parallelism. Traditionally, ASICs have been designed to implement&lt;br /&gt;
specific functionality with high performance and low power constraints. Recently, coarse-grained&lt;br /&gt;
reconfigurable array architectures have been proposed as flexible but still high performance alternatives.&lt;br /&gt;
It is therefore expected that the DSP computing system, increasingly parallel and reconfigurable, will be&lt;br /&gt;
one of the dominating parts in OEM equipments in 2020 because it maximally exposes opportunities of&lt;br /&gt;
parallelization. In this project, we address reconfigurable array processor architectures as well as software&lt;br /&gt;
tools for their programming. A massively parallel execution platform with powerful computing nodes and&lt;br /&gt;
hierarchical interconnection structure suitable for streaming applications will be developed and studied.&lt;br /&gt;
The distinct features of our software development approach are the use of the CAL language for&lt;br /&gt;
programming of these architectures as well as the development and use of tools for timing and energy&lt;br /&gt;
analysis at early design stages. Combining both hardware and software experts in the same project&lt;br /&gt;
provides a strong basis for covering the whole spectrum of this new technology.&lt;br /&gt;
|LogotypeFile=HiPEClogotype.png&lt;br /&gt;
|ProjectResponsible=Veronica Gaspes&lt;br /&gt;
|FundingMSEK=32.3&lt;br /&gt;
|ProjectStart=2011/01/01&lt;br /&gt;
|ProjectEnd=2015/12/31&lt;br /&gt;
|Lctitle=No&lt;br /&gt;
}}&lt;br /&gt;
{{AssignProjPartner&lt;br /&gt;
|projectpartner=Lund University&lt;br /&gt;
}}&lt;br /&gt;
{{AssignProjPartner&lt;br /&gt;
|projectpartner=Linköping University&lt;br /&gt;
}}&lt;br /&gt;
__NOTOC__&lt;br /&gt;
{{ShowResearchProject}}&lt;br /&gt;
== External web ==&lt;br /&gt;
http://hipec.cs.lth.se/&lt;/div&gt;</summary>
		<author><name>Slawek</name></author>	</entry>

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