https://wiki.hh.se/ceres/index.php?action=history&feed=atom&title=Publications%3AProcess_algebraic_verification_of_SystemC_codes 2026-05-23T15:33:01Z Revision history for this page on the wiki MediaWiki 1.22.6 https://wiki.hh.se/ceres/index.php?title=Publications:Process_algebraic_verification_of_SystemC_codes&diff=4120&oldid=prev 2014-06-26T03:43:28Z

<p>Created page with &quot;&lt;div style=&#039;display: none&#039;&gt; == Do not edit this section == &lt;/div&gt; {{PublicationSetupTemplate|Author=H. Hojjat, Mohammad Reza Mousavi, M. Sirjani |PID=584683 |Name=Hojjat, H. (...&quot;</p> <p><b>New page</b></p><div>&lt;div style='display: none'&gt;<br /> == Do not edit this section ==<br /> &lt;/div&gt;<br /> {{PublicationSetupTemplate|Author=H. Hojjat, Mohammad Reza Mousavi, M. Sirjani<br /> |PID=584683<br /> |Name=Hojjat, H. (University of Tehran and Institute for Studies in Theoretical Physics and Mathematics, Iran);Mousavi, Mohammad Reza [mohmou] (Eindhoven University of Technology, The Netherlands);Sirjani, M. (University of Tehran and Institute for Studies in Theoretical Physics and Mathematics, Iran)<br /> |Title=Process algebraic verification of SystemC codes<br /> |PublicationType=Conference Paper<br /> |ContentType=Refereegranskat<br /> |Language=eng<br /> |Journal=<br /> |JournalISSN=<br /> |Status=<br /> |Volume=<br /> |Issue=<br /> |HostPublication=Application of Concurrency to System Design, 2008. ACSD 2008. 8th International Conference on<br /> |Conference=8th International Conference on Application of Concurrence System Design, Xian, PEOPLES R CHINA, JUN 23-27, 2008<br /> |StartPage=62<br /> |EndPage=67<br /> |Year=2008<br /> |Edition=<br /> |Pages=<br /> |City=New York<br /> |Publisher=IEEE Press<br /> |Series=International Conference on Application of Concurrency to System Design. Proceedings<br /> |SeriesISSN=1550-4808<br /> |ISBN=978-1-4244-1838-1;978-1-4244-1839-8<br /> |Urls=<br /> |ISRN=<br /> |DOI=http://dx.doi.org/10.1109/ACSD.2008.4574597<br /> |ISI=000260161500011<br /> |PMID=<br /> |ScopusId=2-s2.0-51549092942<br /> |NBN=urn:nbn:se:hh:diva-20504<br /> |LocalId=<br /> |ArchiveNumber=<br /> |Keywords=Algebra;Computer industry;Hardware;Logic;Mathematics;Physics;Reduced order systems;Sequential circuits;Software standards;System-level design<br /> |Categories=Data- och informationsvetenskap (102)<br /> |ResearchSubjects=<br /> |Projects=<br /> |Notes=<br /> |Abstract=&lt;p&gt;SystemC is an IEEE standard system-level language used in hardware/software co-design and has been widely adopted in the industry. This paper describes a formal approach to verifying SystemC codes by providing a mapping to the process algebra mCRL2. The outstanding advantages of mCRL2 are the support for different data types and a powerful tool-set for model reduction and analysis. A tool is implemented to automatically perform the proposed mapping. This translation enabled us to exploit process-algebraic verification techniques to analyze a number of case-studies, including the formal analysis of a single-cycle and a pipelined MIPS processor specified in SystemC.&lt;/p&gt;<br /> |Opponents=<br /> |Supervisors=<br /> |Examiners=<br /> |Patent=<br /> |ThesisLevel=<br /> |Credits=<br /> |Programme=<br /> |Subject=<br /> |Uppsok=<br /> |DefencePlace=<br /> |DefenceLanguage=<br /> |DefenceDate=<br /> |CreatedDate=2013-01-08<br /> |PublicationDate=2013-01-09<br /> |LastUpdated=2013-02-19<br /> |diva=http://hh.diva-portal.org/smash/record.jsf?searchId=1&amp;pid=diva2:584683}}<br /> &lt;div style='display: none'&gt;<br /> <br /> == Keep all hand-made modifications below ==<br /> &lt;/div&gt;{{PublicationDisplayTemplate}}</div>

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