Difference between revisions of "Publications:Admission control for switched real-time Ethernet : scheduling analysis versus network calculus"

From CERES
Jump to: navigation, search
(Created page with "<div style='display: none'> == Do not edit this section == </div> {{PublicationSetupTemplate|Author=Xing Fan, Magnus Jonsson |PID=239985 |Name=Fan, Xing [xifa] (Högskolan i H...")
 
(No difference)

Latest revision as of 04:42, 26 June 2014

Do not edit this section

Keep all hand-made modifications below

Title Admission control for switched real-time Ethernet : scheduling analysis versus network calculus
Author Xing Fan and Magnus Jonsson
Year 2005
PublicationType Conference Paper
Journal
HostPublication Proc. of the Swedish National Computer Networking Workshop (SNCNW’05), Halmstad, Sweden, Nov. 23-24, 2005
DOI
Conference Swedish National Computer Networking Workshop (SNCNW’05), Halmstad, Sweden, Nov. 23-24, 2005
Diva url http://hh.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:239985
Abstract Many approaches have been developed to give an estimation of the upper bound of the end-to-end delay or the response-time for real-time application, e.g., the Network Calculus (NC) model and the scheduling analysis. In this paper, we present an approach based on scheduling analysis to support guaranteed real-time services over standard switched Ethernet. Furthermore, we conduct a comparative study between these two admission control schemes, our novel algorithm and an NC-based algorithm. The simulation analysis shows that our feasibility analysis gives up to 50% higher utilization than the popular NC. Another advantage of our solution is that no additional hardware or software modification of the switch and the underlying standard. In our proposal, the traffic differentiation mechanism introduced by the IEEE 802.1D/Q standard and the standard hardware-implemented First Come First Served (FCFS) priority queuing are used in the switch and the source nodes. We have derived a feasibility analysis algorithm to ensure that the real-time requirements can be met. The algorithm also gives, as a sub-result, the needed buffer space in the end nodes and the switch. Moreover, our feasibility analysis supports variable-sized frames and switches with different bit-rates ports.