HiPEC
High Performance Embedded Computing
| HiPEC | |
| Project start: | |
|---|---|
| 1 January 2011 | |
| Project end: | |
| 31 December 2015 | |
| More info (PDF): | |
| [[media: | pdf]] | |
| Contact: | |
| Veronica Gaspes | |
Involved internal personnel
| |
| |
Involved external personnel
| |
Involved partners
| |
Abstract
Parallelism is the main way to provide significant performance improvement of embedded systems while keeping energy consumption low. Streaming applications are good candidates for parallelization since they are regular and exhibit data parallelism. Traditionally, ASICs have been designed to implement specific functionality with high performance and low power constraints. Recently, coarse-grained reconfigurable array architectures have been proposed as flexible but still high performance alternatives. It is therefore expected that the DSP computing system, increasingly parallel and reconfigurable, will be one of the dominating parts in OEM equipments in 2020 because it maximally exposes opportunities of parallelization. In this project, we address reconfigurable array processor architectures as well as software tools for their programming. A massively parallel execution platform with powerful computing nodes and hierarchical interconnection structure suitable for streaming applications will be developed and studied. The distinct features of our software development approach are the use of the CAL language for programming of these architectures as well as the development and use of tools for timing and energy analysis at early design stages. Combining both hardware and software experts in the same project provides a strong basis for covering the whole spectrum of this new technology.
