Publications:The VEGA moderately parallel MIMD, moderately parallel SIMD, architecture for high performance array signal processing
From CERES
| Title | The VEGA moderately parallel MIMD, moderately parallel SIMD, architecture for high performance array signal processing |
|---|---|
| Author | Mikael Taveniku and Anders Åhlander and Magnus Jonsson and Bertil Svensson |
| Year | 1998 |
| PublicationType | Conference Paper |
| Journal | |
| HostPublication | Proceedings of the first merged International Parallel Processing Symposium & Symposium on Parallel and Distributed Processing : March 30 - April 3, 1998 Orlando, Florida |
| DOI | http://dx.doi.org/10.1109/IPPS.1998.669915 |
| Conference | first merged International Parallel Processing Symposium & Symposium on Parallel and Distributed Processing, March 30 - April 3, 1998 Orlando, Florida |
| Diva url | http://hh.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:239966 |
| Abstract | In array radar signal processing applications, the processing demands range from tens of GFLOPS to several TFLOPS. To address this, as well as the, size and power dissipation issues, a special purpose “array signal processing” architecture is proposed. We argue that a combined MIMD-SIMD system can give flexibility, scalability, and programmability as well as high computing density. The MIMD system level, where SIMD modules are interconnected by a fiber-optic real-time network, provides the high level flexibility while the SIMD module level provides the compute density. In this paper we evaluate different design alternatives and show how the VEGA architecture was derived. By examining the applications and the algorithms used, the SIMD mesh processor is found be sufficient. However, the smaller the meshes are the better is the flexibility and efficiency. Then, based on prototype VLSI implementations and on instruction statistics, we find that a relatively large pipelined processing element maximises the performance per area. It is thereby concluded that the small SIMD mesh processor array with powerful processing elements is the best choice. These observations are further exploited in the design of the single-chip SIMD processor array to be included in the MIMD-style overall system. The system scales from 6.4 GFLOPS to several TFLOPS peak performance. |
