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We would like to integrate an existing network-on-chip written in Chisel, which is a subset of scala, to the rocket chip generator. The rocket chip generator is a tool that supports generation of different architectures based on RISC-V ISA. The tool has a crossbar network for on chip communication. However this is not a feasible structure when the number of cores increase to hundreds. Therefore we plan to replace this network with a scalable 2D mesh network. - Scala knowledge is required as the generator and the network-on-chip are written in Chisel. - Hardware development and/or system-on-chip design knowledge will be helpful. For further questions, the students may contact Suleyman Savas by e-mail: suleyman.savas@hh.se or by visiting E321.
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