Secure IP Core Design Through LLM-Driven Logic Locking
| Title | Secure IP Core Design Through LLM-Driven Logic Locking |
|---|---|
| Summary | [[OneLineSummary::This thesis aims to explore how LLMs can be employed to assist and improve logic locking mechanisms at the ]behavioral levels of hardware design.]] |
| Keywords | |
| TimeFrame | |
| References | |
| Prerequisites | |
| Author | Mahdi Fazeli |
| Supervisor | Mahdi Fazeli |
| Level | Master |
| Status | Open |
As hardware security becomes increasingly critical in modern System-on-Chip (SoC) designs, logic locking has emerged as a promising technique to safeguard intellectual property (IP) against threats such as reverse engineering, hardware Trojans, and counterfeiting. Traditional logic locking methods often rely on complex manual processes and rule-based techniques to insert security features into hardware designs at the Register Transfer Level (RTL) and behavioral levels. With the advent of Large Language Models (LLMs), such as GPT, Lamma, and Gemini, there is potential to automate and enhance the process of logic locking by leveraging the models’ ability to understand, generate, and manipulate code at different abstraction layers.
This thesis aims to explore how LLMs can be employed to assist and improve logic locking mechanisms at the RTL and behavioral levels of hardware design. The research will investigate the capabilities of LLMs in understanding hardware description languages (HDLs) like Verilog and VHDL, and their effectiveness in identifying potential vulnerabilities, suggesting locking strategies, and automatically inserting secure logic locks into hardware designs. Additionally, the thesis will evaluate the efficiency, accuracy, and scalability of LLM-driven logic locking compared to traditional methods, particularly focusing on securing designs against adversarial attacks while maintaining minimal impact on performance and area overhead. The outcome of this research could open new avenues for integrating AI into hardware security, automating logic locking workflows, and enhancing the robustness of SoC designs in complex, distributed environments.
