Modeling of energy consumption on instruction level for modern many-core architecture
| Title | Modeling of energy consumption on instruction level for modern many-core architecture |
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| Summary | Masters Thesis Project |
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| Author | Tomas Nordström, Süleyman Savaş |
| Supervisor | Tomas Nordström, Süleyman Savaş |
| Level | Master |
| Status | Open |
Project description
In order to optimize the energy consumption of a processor, alone or in a many-core system, a model of the consumed energy for each computation is needed. The granularity of this model can be on instruction level, small sections of code (kernels like FFT butterfly operation), or potentially even larger components like single actors in a dataflow programming model. This work involves developing a methodology to assess the energy consumption of a computation, perform measurements on real hardware to base to models on actual data, and then perform evaluation and verification of the models on real multi-core hardware.
References
Lee, Sheayun, et al. "An accurate instruction-level energy consumption model for embedded risc processors." ACM SIGPLAN Notices. Vol. 36. No. 8. ACM, 2001.
Nikolaidis, Spiridon, et al. "Instrumentation set-up for instruction level power modeling." Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. Springer Berlin Heidelberg, 2002. 71-80.
Ibrahim, Mostafa EA, Markus Rupp, and Hossam AH Fahmy. "A precise high-level power consumption model for embedded systems software." EURASIP Journal on Embedded Systems 2011 (2011): 1.
Nikolaidis, Spiridon, et al. "Instruction level energy modeling for pipelined processors." Journal of Embedded Computing 1.3 (2005): 317-324.
