Publications:A Design Methodology for Resource to Performance Tradeoff Adjustment in FPGAs
From CERES
| Title | A Design Methodology for Resource to Performance Tradeoff Adjustment in FPGAs |
|---|---|
| Author | Fahad Islam Cheema and Zain Ul-Abdin and Bertil Svensson |
| Year | 2010 |
| PublicationType | Conference Paper |
| Journal | |
| HostPublication | FPGAworld '10 Proceedings of the 7th FPGAworld Conference |
| DOI | http://dx.doi.org/10.1145/1975482.1975483 |
| Conference | 7th FPGAworld Conference, FPGAworld 2010, Copenhagen, 6 September 2010 |
| Diva url | http://hh.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:345711 |
| Abstract | When implementing computation-intensive algorithms on finegrained parallel architectures, adjustment of resource to performance tradeoff is a big challenge. This paper proposes a methodology for dealing with some of these performance tradeoffs by adjusting parallelism at different levels. In a case study, interpolation kernels are implemented on a fine-grained architecture (FPGA) using a high level language (Mitrion-C). For both cubic and bi-cubic interpolation, one single-kernel, one cross-kernel and two multi-kernel parallel implementations are designed and evaluated. Our results demonstrate that no single level of parallelism can be used for trade-off adjustment. Instead, the appropriate degree of parallelism on each level, according to available resources and the performance requirements of the application, needs to be found. Basing the design on high-level programming simplifies the trade-off process. This research is a step towards automation of the choice of parallelization based on a combination of parallelism levels. |
