Publications:Architectural challenges in memory-intensive, real-time image forming
From CERES
| Title | Architectural challenges in memory-intensive, real-time image forming |
|---|---|
| Author | Anders Åhlander and H. Hellsten and K. Lind and J. Lindgren and Bertil Svensson |
| Year | 2007 |
| PublicationType | Conference Paper |
| Journal | |
| HostPublication | International Conference on Parallel Processing, 2007. ICPP 2007 |
| DOI | http://dx.doi.org/10.1109/ICPP.2007.18 |
| Conference | |
| Diva url | http://hh.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:239178 |
| Abstract | The real-time image forming in future, high-end synthetic aperture radar systems is an example of an application that puts new demands on computer architectures. The initial question is whether it is at all possible to meet the demands with state-of-the-art technology or foreseeable new technology. It is therefore crucial to understand the computational flow, with its associated memory, bandwidth and processing demands. In this paper we analyse the application in order to, primarily, understand the algorithms and identify the challenges they present on a basic architectural level. The processing in the radar system is characterized by working on huge data sets, having complex memory access patterns, and doing real-time compensations for flight path errors. We propose algorithm solutions and execution schemes in interplay with a two-level (coarse-grain/fine-grain) system parallelization approach, and we provide approximate models on which the demands are quantified. In particular, we consider the choice of method for the performance-intensive data interpolations. This choice presents a trade-off problem between computational performance and size of working memory. The results of this "upstream" study will serve as a basis for further, more detailed architecture studies. |
