Integrating a 2D mesh network-on-chip to an architecture generation tool to generate manycore architectures
| Title | Integrating a 2D mesh network-on-chip to an architecture generation tool to generate manycore architectures |
|---|---|
| Summary | Integration of an existing network-on-chip to a tool written in Chisel (scala). |
| Keywords | |
| TimeFrame | |
| References | https://github.com/freechipsproject/rocket-chip
https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html https://www.mdpi.com/2073-431X/7/2/27"https://github.com/freechipsproject/rocket-chip https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html https://www.mdpi.com/2073-431X/7/2/27" cannot be used as a page name in this wiki. |
| Prerequisites | |
| Author | |
| Supervisor | Süleyman Savaş, Zain Ul-Abdin |
| Level | Master |
| Status | Open |
We would like to integrate an existing network-on-chip written in Chisel, which is a subset of scala, to the rocket chip generator. The rocket chip generator is a tool that supports generation of different architectures based on RISC-V ISA. The tool has a crossbar network for on chip communication. However this is not a feasible structure when the number of cores increase to hundreds. Therefore we plan to replace this network with a scalable 2D mesh network.
- Scala knowledge is required as the generator and the network-on-chip are written in Chisel.
- Hardware development and/or system-on-chip design knowledge will be helpful.
For further questions, the students may contact Suleyman Savas by e-mail: suleyman.savas@hh.se or by visiting E321.
