| Abstract
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<p>High-level programming languages … <p>High-level programming languages offer significant expressivitybut provide little or no guarantees about resource use. Resourcebounded languages — such as hardware-description languages —provide strong guarantees about the runtime behavior of computations but often lack mechanisms that allow programmers to writemore structured, modular, and reusable programs. To overcomethis basic tension in language design, recent work advocated the useof Resource-aware Programming (RAP) languages, which take intoaccount the natural distinction between the development platformand the deployment platform for resource-constrained software.This paper investigates the use of RAP languages for the generation of combinatorial circuits. The key challenge that we encounteris that the RAP approach does not safely admit a mechanism to express a posteriori (post-generation) optimizations. The paper proposes and studies the use of abstract interpretation to overcome thisproblem. The approach is illustrated using an in-depth analysis ofthe Fast Fourier Transform (FFT). The generated computations arecomparable to those generated by FFTW.</p>able to those generated by FFTW.</p>
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| Author
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Oleg Kiselyov +
, Kedar N. Swadi +
, Walid Taha +
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| Conference
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EMSOFT'04. International Conference on Embedded Software and Systems.
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| Diva
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http://hh.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:588274
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| PublicationType
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Conference Paper +
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| Title
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A Methodology for Generating Verified Combinatorial Circuits +
|
| Year
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2004 +
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| Has queryThis property is a special property in this wiki.
|
Publications:A Methodology for Generating Verified Combinatorial Circuits +
, Publications:A Methodology for Generating Verified Combinatorial Circuits +
, Publications:A Methodology for Generating Verified Combinatorial Circuits +
, Publications:A Methodology for Generating Verified Combinatorial Circuits +
, Publications:A Methodology for Generating Verified Combinatorial Circuits +
, Publications:A Methodology for Generating Verified Combinatorial Circuits +
, Publications:A Methodology for Generating Verified Combinatorial Circuits +
, Publications:A Methodology for Generating Verified Combinatorial Circuits +
, Publications:A Methodology for Generating Verified Combinatorial Circuits +
, Publications:A Methodology for Generating Verified Combinatorial Circuits +
|
| Categories |
Publication +
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| Modification dateThis property is a special property in this wiki.
|
26 June 2014 03:44:55 +
|
