Abstract
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<p>We present a formal semantics for … <p>We present a formal semantics for a subset of Verilog, commonly used to describe cell libraries, in terms of transition systems. Such transition systems can serve as input to symbolic model checking, for example equivalence checking with a transistor netlist description. We implement our formal semantics as an encoding from the subset of Verilog to the input language of the SMV model-checker. Experiments show that this approach is able to verify complete cell libraries.</p> verify complete cell libraries.</p>
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Author
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Matthias Raffelsieper +
, Jan-Willem Roorda +
, Mohammad Reza Mousavi +
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Conference
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9th International Conference on Application of Concurrency to System Design, Augsburg, GERMANY, JUL 01-03, 2009
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DOI
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http://dx.doi.org/10.1109/ACSD.2009.18 +
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Diva
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http://hh.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:584680
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EndPage
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137 +
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HostPublication
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2009 Ninth International Conference on Application of Concurrency to System Design : Proceedings +
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PublicationType
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Conference Paper +
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Publisher
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IEEE Computer Society +
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StartPage
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128 +
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Title
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Model checking Verilog descriptions of cell libraries +
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Year
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2009 +
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Has queryThis property is a special property in this wiki.
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Publications:Model checking Verilog descriptions of cell libraries +
, Publications:Model checking Verilog descriptions of cell libraries +
, Publications:Model checking Verilog descriptions of cell libraries +
, Publications:Model checking Verilog descriptions of cell libraries +
, Publications:Model checking Verilog descriptions of cell libraries +
, Publications:Model checking Verilog descriptions of cell libraries +
, Publications:Model checking Verilog descriptions of cell libraries +
, Publications:Model checking Verilog descriptions of cell libraries +
, Publications:Model checking Verilog descriptions of cell libraries +
, Publications:Model checking Verilog descriptions of cell libraries +
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Categories |
Publication +
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Modification dateThis property is a special property in this wiki.
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26 June 2014 03:43:50 +
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