| Abstract
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<p>Modern hardware description langu … <p>Modern hardware description languages support code-generation constructs like <strong>generate/endgenerate</strong> in Verilog. These constructs are intended to describe regular or parameterized hardware designs and, when used effectively, can make hardware descriptions shorter, more understandable, and more reusable. In practice, however, designers avoid these constructs because it is difficult to understand and predict the properties of the generated code. Is the generated code even type safe? Is it synthesizable? What physical resources (e.g. combinatorial gates and flip-flops) does it require? It is often impossible to answer these questions without first generating the fully-expanded code. In the Verilog and VHDL communities, this generation process is referred to as elaboration.</p><p>This paper proposes a disciplined approach to elaboration in Verilog. By viewing Verilog as a statically typed two-level language, we are able to reflect the distinction between values that are known at elaboration time and values that are part of the circuit computation. This distinction is crucial for determining whether abstractions such as iteration and module parameters are used in a synthesizable manner. To illustrate this idea, we develop a core calculus for Verilog that we call Featherweight Verilog (FV) and an associated static type system. We formally define a preprocessing step analogous to the elaboration phase of Verilog, and the kinds of errors that can occur during this phase. Finally, we show that a well-typed design cannot cause preprocessing errors, and that the result of its expansion is always a synthesizable circuit.</p> always a synthesizable circuit.</p>
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| Author
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Jennifer Gillenwater +
, Gregory Malecha +
, Cherif Salama +
, Angela Yun Zhu +
, Walid Taha +
, Jim Grundy +
, John O'Leary +
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| Conference
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2008 ACM SIGPLAN Symposium on Partial Evaluation and Semantics-Based Program Manipulation, San Francisco, California, USA, January 7-8, 2008
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| DOI
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http://dx.doi.org/10.1145/1328408.1328416 +
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| Diva
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http://hh.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:396139
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| EndPage
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20 +
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| HostPublication
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PEPM '08 : proceedings of the 2008 ACM SIGPLAN Symposium on Partial Evaluation and Semantics-Based Program Manipulation, San Francisco, California, USA, January 7-8, 2008 +
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| PublicationType
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Conference Paper +
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| Publisher
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ACM Press +
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| StartPage
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13 +
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| Title
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Synthesizable high level hardware descriptions : using statically typed two-level languages to guarantee verilog synthesizability +
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| Year
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2008 +
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| Has queryThis property is a special property in this wiki.
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Publications:Synthesizable high level hardware descriptions : using statically typed two-level languages to guarantee verilog synthesizability +
, Publications:Synthesizable high level hardware descriptions : using statically typed two-level languages to guarantee verilog synthesizability +
, Publications:Synthesizable high level hardware descriptions : using statically typed two-level languages to guarantee verilog synthesizability +
, Publications:Synthesizable high level hardware descriptions : using statically typed two-level languages to guarantee verilog synthesizability +
, Publications:Synthesizable high level hardware descriptions : using statically typed two-level languages to guarantee verilog synthesizability +
, Publications:Synthesizable high level hardware descriptions : using statically typed two-level languages to guarantee verilog synthesizability +
, Publications:Synthesizable high level hardware descriptions : using statically typed two-level languages to guarantee verilog synthesizability +
, Publications:Synthesizable high level hardware descriptions : using statically typed two-level languages to guarantee verilog synthesizability +
, Publications:Synthesizable high level hardware descriptions : using statically typed two-level languages to guarantee verilog synthesizability +
, Publications:Synthesizable high level hardware descriptions : using statically typed two-level languages to guarantee verilog synthesizability +
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| Categories |
Publication +
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| Modification dateThis property is a special property in this wiki.
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26 June 2014 03:44:53 +
|
