WG211/M11Puschel

Computer Generation of IP Cores by Markus Puschel

IP cores are in hardware design the rough equivalent of libraries in software development: Reusable components that are often optimized for high performance. Examples include arithmetic units, coders and decoders, transforms, sorters, and many others. Similar to library development, performance optimization of IP cores is usually hard. Different from library development, there is usually not one fastest solution, but a set of solutions with Pareto-optimal performance-area trade-offs. In this talk we present a generator, based on the Spiral framework, for certain types of IP cores including Fourier transforms and sorters. The input is a function specification. First various algorithms are generated that are expressed in a domain-specific language. Then, architectural decisions are made using a tag-based rewriting system. Finally, a domain-specific compiler translates into RTL Verilog. The generator thus allows for systematic design space exploration and extraction of the Pareto-optimal points. The generated cores are competitive with hand-implemented designs while offering a much larger area-performance trade-off.