| Abstract
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<p>Module paths are often used to sp … <p>Module paths are often used to specify the delays of cells in a Verilog cell library description, which define the propagation delay for an event from an input to an output. Specifying such paths manually is an error prone task; a forgotten path is interpreted as a zero delay, which can cause further flaws in the subsequent design steps. Moreover, one can specify superfluous module paths, i.e., module paths that can never occur in any practical run of the model and hence, make excessive restrictions on the subsequent design decision. This paper presents a method to check whether the given module paths are reflected in the functional implementation. Complementing this check, we also present a method to derive module paths from a functional description of a cell. © 2010 EDAA.</p>cription of a cell. © 2010 EDAA.</p>
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| Author
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M. Raffelsieper +
, Mohammad Reza Mousavi +
, C. Strolenberg +
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| Conference
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Design, Automation and Test in Europe Conference & Exhibition 2010, Dresden, Germany, March 8-12, 2010
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| DOI
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http://dx.doi.org/10.1109/DATE.2010.5457050 +
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| Diva
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http://hh.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:584494
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| EndPage
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1511 +
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| HostPublication
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Design, Automation and Test in Europe Conference & Exhibition 2010 (DATE’10, Dresden, Germany, March 8-12, 2010) +
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| PublicationType
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Conference Paper +
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| Publisher
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IEEE Computer Society +
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| Series
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Design, Automation, and Test in Europe Conference and Exhibition. Proceedings +
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| StartPage
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1506 +
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| Title
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Checking and deriving module paths in Verilog cell library descriptions +
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| Year
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2010 +
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| Has queryThis property is a special property in this wiki.
|
Publications:Checking and deriving module paths in Verilog cell library descriptions +
, Publications:Checking and deriving module paths in Verilog cell library descriptions +
, Publications:Checking and deriving module paths in Verilog cell library descriptions +
, Publications:Checking and deriving module paths in Verilog cell library descriptions +
, Publications:Checking and deriving module paths in Verilog cell library descriptions +
, Publications:Checking and deriving module paths in Verilog cell library descriptions +
, Publications:Checking and deriving module paths in Verilog cell library descriptions +
, Publications:Checking and deriving module paths in Verilog cell library descriptions +
, Publications:Checking and deriving module paths in Verilog cell library descriptions +
, Publications:Checking and deriving module paths in Verilog cell library descriptions +
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| Categories |
Publication +
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| Modification dateThis property is a special property in this wiki.
|
26 June 2014 03:43:47 +
|
