Author Zain Ul-Abdin
From CERES
A list of all pages that have property "Author" with value "Zain Ul-Abdin"
Previous Results 1– 20 Next (20 | 50 | 100 | 250 | 500)
Previous Results 1– 20 Next (20 | 50 | 100 | 250 | 500)
- Publications:A Communication Library for Mapping Dataflow Applications on Manycore Architectures +
- Publications:A Communication Library for Mapping Dataflow Applicationson Manycore Architectures +
- Publications:A Design Methodology for Resource to Performance Tradeoff Adjustment in FPGAs +
- Publications:A Study of Design Efficiency with a High-Level Language for FPGAs +
- Publications:An Evaluation of Code Generation of Dataflow Languages on Manycore Architectures +
- Publications:An Evaluation of High-Performance Embedded Processing on MPPAs +
- Publications:Compiling Stream-Language Applications to a Reconfigurable Array Processor +
- Publications:Energy-Efficient Synthetic-Aperture Radar Processing on a Manycore Architecture +
- Publications:Evolution in Architectures and Programming Methodologies of Coarse-Grained Reconfigurable Computing +
- Publications:Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing +
- Publications:High-level programming of coarse-grained reconfigurable architectures +
- Publications:Managing Dynamic Reconfiguration for Fault-tolerance on a Manycore Architecture +
- Publications:Mapping Occam-pi programs to a Manycore Architecture +
- Publications:Occam-pi as a High-level Language for Coarse-Grained Reconfigurable Architectures +
- Publications:Occam-pi for Programming of Massively Parallel Reconfigurable Architectures +
- Publications:Parallelization of the Estimation Algorithm of the 3D Structure Tensor +
- Publications:Programming Real-time Autofocus on a Massively Parallel Reconfigurable Architecture using Occam-pi +
- Publications:Programming Real-time Image Processing for Manycores in a High-level Language +
- Publications:Programming of Coarse-Grained Reconfigurable Architectures +
- Publications:Real-time Radar Signal Processing on Massively Parallel Processor Arrays +
