Modification date 26 June 2014 03:44:54
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A list of all pages that have property "Modification dateThis property is a special property in this wiki." with value "26 June 2014 03:44:54".
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- Publications:Implicitly Heterogeneous Multi-Stage Programming for FPGAs + (26 June 2014 03:44:48)
- Publications:Implementing Multi-stage Languages Using ASTs, Gensym, and Reflection + (26 June 2014 03:44:48)
- Publications:DSL Implementation in MetaOCaml, Template Haskell, and C++ + (26 June 2014 03:44:49)
- Publications:Multi-Stage Programming for High-Level Description of Circuit Families + (26 June 2014 03:44:49)
- Publications:Implicitly Heterogeneous Multi-stage Programming + (26 June 2014 03:44:50)
- Publications:Implicitly Heterogeneous Multi-Stage Programming + (26 June 2014 03:44:50)
- Publications:Concoqtion : Indexed Types Now! + (26 June 2014 03:44:51)
- Publications:The Semantics of Graphical Languages + (26 June 2014 03:44:51)
- Publications:Macros as Multi-Stage Computations : Type-Safe, Generative, Binding Macros in MacroML + (26 June 2014 03:44:52)
- Publications:Synthesizable high level hardware descriptions : using statically typed two-level languages to guarantee verilog synthesizability + (26 June 2014 03:44:53)
- Publications:Synthesizable High Level Hardware Descriptions + (26 June 2014 03:44:53)
- Publications:E-FRP with Priorities + (26 June 2014 03:44:54)
- Publications:Reasoning About Multi-Stage Programs + (26 June 2014 03:44:54)
- Publications:Relating FFTW and Split-Radix + (26 June 2014 03:44:55)
- Publications:A Methodology for Generating Verified Combinatorial Circuits + (26 June 2014 03:44:55)
- Publications:Preface + (26 June 2014 03:44:56)
- Publications:Idealized MetaML : Simpler, and More Expressive + (26 June 2014 03:44:57)
- Publications:Towards a Primitive Higher Order Calculus of Broadcasting Systems + (26 June 2014 03:44:57)
- Publications:Tagless Staged Interpreters for Typed Languages + (26 June 2014 03:44:58)
- Publications:Static Consistency Checking for Verilog Wire Interconnects : Using Dependent Types to Check the Sanity of Verilog Descriptions + (26 June 2014 03:44:58)
- Publications:Exploring the Design Space of Higher-Order Casts + (26 June 2014 03:44:59)
- Publications:Static Consistency Checking for Verilog Wire Interconnects : Using dependent types to check the sanity of verilog descriptions + (26 June 2014 03:44:59)
